The short answer: a digital electronics interview checks whether your fundamentals are solid: number systems and 2’s complement, Boolean algebra and K-maps, combinational blocks like muxes and adders, sequential logic like flip-flops, counters and FSMs, and basic timing (setup, hold, metastability). Most of the questions below are short, but interviewers follow up with “why?”, so understand each answer rather than memorising it.
Almost every VLSI interview I know of starts here, whether the role is design, verification, physical design or DFT. It’s the first filter: if the basics are shaky, the interviewer rarely moves on to the harder topics.
I’ve grouped the questions the way the round usually flows, from easy to harder. Where a topic has its own detailed post on this site, I’ve linked it.
- What this round covers
- Number systems and Boolean logic
- Combinational circuits
- Sequential circuits
- Timing and CMOS basics
- How I’d prepare for this round
Table of Contents
Part 1: What this round covers
For freshers this round can take the whole interview. For experienced roles it’s usually a 10 to 15 minute warm-up before RTL or domain questions.
Part 2: Number systems and Boolean logic
1. What is 2’s complement, and why do we use it?
To get the 2’s complement of a number, invert all bits and add 1. We use it because there is only one representation of zero, and the same adder works for both addition and subtraction. An n-bit 2’s complement number ranges from −2n−1 to 2n−1−1, so 8 bits cover −128 to 127.
2. How do you detect overflow in signed addition?
Overflow happens when you add two numbers with the same sign and the result has the opposite sign. In hardware it’s simply the XOR of the carry into the MSB and the carry out of the MSB.
3. What is Gray code, and where is it used?
In Gray code, consecutive values differ in exactly one bit. That makes it safe for values that are sampled asynchronously, which is why async FIFO pointers use it. It’s also used in rotary encoders and to order K-map rows and columns.
// binary to Gray
assign gray = bin ^ (bin >> 1);
// Gray to binary: each bit is the XOR of all higher Gray bits
always @(*) begin
bin[N-1] = gray[N-1];
for (i = N-2; i >= 0; i = i - 1)
bin[i] = bin[i+1] ^ gray[i];
end4. Why are NAND and NOR called universal gates?
Because you can build any Boolean function using only one of them. With NAND: tie both inputs together to get NOT, add a NOT after a NAND to get AND, and NAND the inverted inputs to get OR (De Morgan). See logic gates for the full set.
5. State De Morgan’s theorems.
(A·B)′ = A′ + B′ and (A + B)′ = A′·B′. In words: break the bar and change the operator. Interviewers love asking you to convert an AND-OR circuit to NAND-NAND using this.
6. How many 2-input NAND gates do you need for an XOR?
Four. The first NAND takes A and B; its output goes into two more NANDs, one with A and one with B; a fourth NAND combines those two.
7. What are don’t-care conditions in a K-map?
Input combinations that can never occur, or whose output doesn’t matter. You can treat each one as 0 or 1, whichever gives you bigger groups and a simpler expression. More in my K-map guide.
8. What is the difference between SOP and POS?
Sum of products is an OR of AND terms (built from the 1s of the truth table) and maps directly to NAND-NAND logic. Product of sums is an AND of OR terms (built from the 0s) and maps to NOR-NOR logic.
Part 3: Combinational circuits
9. How do you implement AND, OR and NOT with a 2:1 mux?
With y = s ? i1 : i0:
- NOT x: s = x, i0 = 1, i1 = 0
- x AND y: s = x, i0 = 0, i1 = y
- x OR y: s = x, i0 = y, i1 = 1
Since you can build NOT and AND, the 2:1 mux is also universal. See multiplexers.
10. How do you build a 4:1 mux from 2:1 muxes?
Three of them. Two 2:1 muxes select with s[0] between (i0, i1) and (i2, i3); a third selects between their outputs with s[1].
11. How can you implement any n-variable function with a 2n−1:1 mux?
Use n−1 variables as the select lines. For each select combination, the remaining variable decides the output, so each data input is 0, 1, x or x′.
12. What are the equations of a full adder?
Sum = A ⊕ B ⊕ Cin and Cout = A·B + Cin·(A ⊕ B). A full adder can be built from two half adders and an OR gate. More in half and full adders.
13. Why is a carry-lookahead adder faster than a ripple-carry adder?
In a ripple-carry adder each carry waits for the previous one, so delay grows linearly with width. A carry-lookahead adder computes generate (G = A·B) and propagate (P = A ⊕ B) for every bit and uses Ci+1 = Gi + Pi·Ci to compute carries in parallel, so delay grows roughly with log(n), at the cost of more area.
14. What is the difference between an encoder and a priority encoder?
A plain encoder assumes only one input is active at a time. A priority encoder handles several active inputs by giving the output for the highest-priority one, and usually adds a “valid” output for the all-zero case.
15. What is a static hazard, and how do you remove it?
A static-1 hazard is a brief glitch to 0 on an output that should stay at 1, caused by different path delays when an input changes. On a K-map it shows up as two adjacent groups that don’t overlap; adding the redundant consensus term covering both removes it. In synchronous designs these glitches are usually harmless because outputs are sampled at the clock edge, but they matter on clocks, asynchronous resets and for power.
Part 4: Sequential circuits
16. What is the difference between a latch and a flip-flop?
A latch is level-sensitive: while enabled it is transparent and the output follows the input. A flip-flop is edge-triggered: it samples the input only at the clock edge. Most ASIC designs use flip-flops because timing is much easier to analyse. See latches vs flip-flops.
17. Why is S = R = 1 not allowed in a NOR SR latch?
Both outputs are forced to 0, so Q and Q′ are no longer complements. Worse, if S and R are released together, the latch can settle either way or oscillate, so the next state is unpredictable.
18. How do you convert a D flip-flop into a T or JK flip-flop?
For T: D = T ⊕ Q. For JK: D = J·Q′ + K′·Q. Both are just next-state logic in front of a D flip-flop, which is how real designs build them. See D flip-flop.
19. Synchronous or asynchronous reset: which would you use?
A synchronous reset is sampled on the clock edge, so it needs a running clock and behaves like any other data input. An asynchronous reset acts immediately, even without a clock. A common choice is asynchronous assertion with synchronous de-assertion, using a reset synchroniser, so release can’t cause metastability.
20. How do you divide a clock by 2? And by 3 with 50% duty cycle?
Divide by 2: feed Q′ back to D of a flip-flop. Divide by 3 with 50% duty: build a mod-3 counter on the rising edge, delay one of its outputs by half a cycle with a falling-edge flop, and OR the two. In real chips I’d prefer a clock enable over a divided clock where possible. See counters and clock dividers.
21. What is the difference between a ring counter and a Johnson counter?
With N flip-flops, a ring counter circulates a single 1 and has N states. A Johnson (twisted-ring) counter feeds back the inverted output and has 2N states.
22. What is the difference between Mealy and Moore machines?
Moore outputs depend only on the state, so they are stable for a whole cycle. Mealy outputs depend on the state and the inputs, so they react a cycle earlier and often need fewer states, but can glitch with the inputs. See Mealy vs Moore.
23. Design a Mealy detector for the overlapping sequence 101.
Three states: S0 (nothing useful seen), S1 (seen 1), S2 (seen 10).
- S0: input 1 → S1, input 0 → S0
- S1: input 0 → S2, input 1 → S1
- S2: input 1 → output 1 and go to S1 (the last 1 starts the next match); input 0 → S0
A Moore version needs a fourth state to hold the output.
Part 5: Timing and CMOS basics
24. What are setup time and hold time?
Setup time is how long data must be stable before the clock edge; hold time is how long it must stay stable after the edge. Break either and the flop may capture the wrong value or go metastable.
25. How do you find the maximum clock frequency of a circuit?
For a path between two flops, the clock period must satisfy:
T_clk >= t_clk-to-q + t_comb(max) + t_setup - t_skewwhere skew is the capture clock arrival minus the launch clock arrival. The hold check is tclk-to-q + tcomb(min) ≥ thold + tskew. fmax is 1 over the smallest Tclk that meets setup on the worst path.
26. Does clock skew help or hurt?
Both. If the capture clock arrives later than the launch clock (positive skew), setup gets easier but hold gets harder. Negative skew does the opposite.
27. Why is a hold violation worse than a setup violation?
A setup violation can be fixed after silicon by slowing the clock. A hold violation doesn’t depend on the clock period, so the chip fails at any frequency.
28. What is metastability, and how do you reduce the risk?
If a flop’s input changes inside its setup-hold window, the output can hang between 0 and 1 for an unpredictable time. You can’t prevent it when signals cross between unrelated clocks, but a two-flop synchroniser gives it a full cycle to resolve, which makes failures extremely rare. See clock domain crossing.
29. How does a CMOS inverter work?
A PMOS transistor pulls the output up to VDD and an NMOS pulls it down to ground. When the input is high the NMOS is on and the PMOS is off, so the output is low, and the other way round. In steady state one of them is always off, so ideally there is no static current.
30. Why is NAND preferred over NOR in CMOS?
A NOR gate has its PMOS transistors in series. Holes are slower than electrons, so PMOS devices are already sized wider, and putting them in series makes a NOR gate larger and slower. A NAND puts the faster NMOS devices in series instead.
31. Where does power go in a CMOS circuit?
Dynamic switching power, roughly α·C·V2·f; short-circuit power during transitions; and leakage. Lowering voltage helps the most because of the V2 term, and clock gating cuts α for idle logic.
Part 6: How I’d prepare for this round
- Derive, don’t memorise. If you can derive the full adder or the flip-flop conversions on paper, follow-up questions won’t worry you.
- Draw timing diagrams. Counters, shift registers and FSM outputs, cycle by cycle.
- Practise out loud. Explaining setup and hold clearly is a skill in itself.
- Write the RTL too. Many interviewers ask you to code the mux, counter or FSM you just drew.
Practise this on VLSI Forge
I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.
FAQ
Is this round only for freshers?
It’s the main round for freshers and interns, but experienced candidates usually get a shorter version as a warm-up, especially the timing questions.
Which book should I use to revise digital electronics?
Digital Design by M. Morris Mano and Michael Ciletti covers almost everything here. For timing, any good STA introduction helps.
How many questions should I prepare?
Depth matters more than count. If you can explain the 31 above and their follow-ups, you’re well prepared for most fresher rounds.
Do I need to know CMOS transistor-level design for an RTL role?
Only the basics: the inverter, NAND/NOR structure, and where power goes. Deeper circuit questions are for analog and custom design roles.
