The short answer: Every routed wire has parasitic resistance and capacitance, extracted from the layout into a SPEF file using the foundry’s RC models. At advanced nodes, much of a wire’s capacitance is coupling to its neighbours, which causes crosstalk: an aggressor switching in the opposite direction slows the victim (hurting setup), switching in the same direction speeds it up (hurting hold), and a quiet victim can get a noise glitch. Signal-integrity-aware STA includes these effects, and fixes include spacing, shielding, layer changes, buffering and upsizing.
Before routing, timing tools estimate wires. After routing, they use the real thing, and the numbers almost always get worse. This post explains where the extra delay comes from and how crosstalk is analysed and fixed. It combines my older posts on crosstalk and parasitics and on crosstalk and signal noise.
- What a wire really is
- Parasitic extraction
- Crosstalk delay and noise
- Fixing crosstalk
- Other signal integrity effects
Table of Contents
Part 1: What a wire really is
Part 2: Parasitic extraction
After routing, an extraction tool (StarRC, Quantus or similar) reads the layout and the foundry’s RC technology files and produces a parasitic netlist, usually in SPEF format, for every net. It’s run at several corners (for example Cmax, Cmin, RCmax, RCmin) because metal thickness and width vary with manufacturing. STA then uses this to compute real wire delays.
- Resistance increases sharply on thin lower metals at advanced nodes, so long nets belong on upper layers.
- Coupling capacitance grows as wires get closer, and can be more than half of a wire’s total capacitance.
- Via resistance matters more at every new node.
Part 3: Crosstalk delay and noise
| Effect | When it happens | What it breaks |
|---|---|---|
| Delta delay (slower) | Aggressor switches opposite to the victim in the same window | Setup on the victim path |
| Delta delay (faster) | Aggressor switches in the same direction | Hold on the victim path |
| Noise glitch | Victim is quiet; aggressor switches | Functional errors if a flop or latch captures it |
STA tools consider timing windows: an aggressor only matters if it can switch while the victim is switching. That’s why asynchronous clocks are treated as able to switch at any time.
Part 4: Fixing crosstalk
- Increase spacing between victim and aggressor, or route with non-default rules.
- Shield sensitive nets (especially clocks) with ground or power wires.
- Move one of the nets to a different layer or reroute it.
- Upsize the victim’s driver or add a buffer to shorten the coupled length.
- Slow down the aggressor’s transition where it doesn’t need to be fast.
Part 5: Other signal integrity effects
IR drop on the supply also changes cell delays, and modern sign-off can include voltage-aware timing. Antenna effects during manufacturing are handled in physical verification, and supply noise in IR drop and electromigration.
Practise this on VLSI Forge
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Physical Design problems · Static Timing Analysis problems
Previous in my physical design series: Routing. Next: Timing closure and ECOs.
FAQ
What are parasitics in VLSI?
The unintended resistance and capacitance of wires and vias, extracted from the layout and used to compute real delays.
What is SPEF?
Standard Parasitic Exchange Format: the file that carries extracted resistance and capacitance of each net to STA and other tools.
How does crosstalk affect setup and hold?
An aggressor switching opposite to the victim slows it and hurts setup; switching in the same direction speeds it up and hurts hold.
How do you fix crosstalk?
Spacing, shielding, rerouting on another layer, upsizing the victim driver, buffering, or slowing the aggressor.
