Browsing: HDL design

Verilog

Verilog System Tasks: $display, $monitor, $readmemh and More

Raju Gorla2 August 2026

The Verilog system tasks I actually use: $display vs $strobe vs $monitor, format specifiers, $finish, file I/O, $readmemh, waveform dumping, $random and $clog2.

Verilog

Tasks and Functions in Verilog: Differences, Arguments and Examples

Raju Gorla31 July 2026

Verilog tasks vs functions explained with examples: return values, timing controls, synthesis, how arguments are passed, and static vs automatic.

Verilog

Verilog Modules, Ports and Instantiation: Building a Hierarchy

Raju Gorla21 July 2026

How to define Verilog modules, declare ports, instantiate modules with named connections and parameters, build a hierarchy, and use generate for repeated instances.