I’ve compiled 40 Ethernet interview questions from network design, verification, and deployment experience. If you’re interviewing for an Ethernet MAC design role, a network PHY position, or a platform validation job at companies like Broadcom, Cisco, Intel, Arista, or Juniper, you’ll hit most of these topics. The key is understanding both the frame format and the physical layer—they’re inseparable.
💡 This is for: Hardware engineers, network designers, ASIC validation engineers, and anyone interviewing for Ethernet MAC/PHY roles. Also useful for platform integration engineers at hyperscalers.
Table of Contents
Quick Navigation
- Section 1: Ethernet Fundamentals (Q1–Q10)
- Section 2: PHY & MAC Architecture (Q11–Q20)
- Section 3: 10G+ Ethernet (Q21–Q30)
- Section 4: Design & Verification (Q31–Q40)
- Most-Asked Topics by Company
Section 1: Ethernet Fundamentals (Q1–Q10)
Q1. What is the Ethernet frame format? Explain every field.
An Ethernet frame consists of: Preamble (7 bytes, 10101010…), SFD (1 byte, 10101011), Destination MAC (6 bytes), Source MAC (6 bytes), Type/Length (2 bytes), Payload (46–1500 bytes), FCS (4 bytes, CRC). Total: 64–1518 bytes (or up to 1522 with VLAN).
Preamble and SFD are used for clock recovery and frame detection—the PHY strips them before sending to the MAC. Type field is 0x0800 for IP, 0x0806 for ARP. FCS is a 32-bit CRC (polynomial 0x04C11DB7) computed over DA, SA, Type, and Payload. Here’s the layout:
+--------+-----+------+------+------+------+-------+-----+ |Preamble| SFD | DA | SA | Type |Payload| FCS |Gap | | 7 B | 1B | 6B | 6B | 2B |46-1500|4B |12B | +--------+-----+------+------+------+------+-------+-----+
💡 Tip: The Preamble and SFD are not counted in the frame length—they’re part of the physical layer. The minimum payload is 46 bytes; anything less requires padding. Interviewers often ask why 46 bytes is the minimum—it’s to ensure minimum frame time at 10Mbps (60 bytes × 8 bits = 480 bits at 10MHz ≈ 48 microseconds), preventing collision detection issues.
Q2. What is CSMA/CD? Why is it irrelevant in modern full-duplex Ethernet?
CSMA/CD (Carrier Sense, Multiple Access, Collision Detection) was the MAC protocol for shared-medium Ethernet (hubs, half-duplex links). A node would: sense the carrier (listen for ongoing transmission), wait if busy, transmit if idle, detect collision (signal bouncing back), and back off with exponential delay before retrying.
It’s irrelevant now because modern Ethernet is full-duplex point-to-point (switch to NIC, no shared medium). Both sides can transmit simultaneously without collision. There’s no carrier to sense, no collision to detect. Full-duplex Ethernet (802.3ab, 802.3an, etc.) completely bypasses CSMA/CD. If you encounter CSMA/CD questions, the interviewer is testing whether you understand that Ethernet evolved.
📌 Note: Half-duplex Ethernet is essentially obsolete (last seen in Fast Ethernet hubs ~2000s). Full-duplex has been standard for 20+ years, but legacy devices and interview questions still reference CSMA/CD.
Q3. What is the MAC address structure? What does the OUI represent?
A MAC address is 48 bits (6 bytes): first 3 bytes = OUI (Organizationally Unique Identifier), last 3 bytes = NIC-specific (vendor-assigned). The first byte also contains two flags: bit 0 = Unicast (0) / Multicast (1), bit 1 = Unicast (0) / Locally Administered (1).
The OUI is a manufacturer identifier registered with IEEE. For example, 00:1A:2B is Intel, 00:50:F2 is Microsoft. The broadcast address FF:FF:FF:FF:FF:FF is all 1s (all receivers). Multicast addresses have the group bit set (first byte LSB = 1)—for example, 01:00:5E:00:00:01 is reserved for IGMP (IP Multicast).
Q4. How does auto-negotiation work? What happens if it fails?
Auto-negotiation uses electrical pulses (Fast Link Pulses, FLP) on the idle pair(s) to communicate speed and duplex capabilities between two Ethernet devices. Each side transmits a bitmap indicating supported speeds (10M, 100M, 1G, etc.) and duplex modes. After negotiation, both settle on the highest common speed.
If negotiation fails (no pulses detected, corrupted pulses), the MAC defaults to a fallback (typically 100M half-duplex on older devices, more conservative fallbacks on modern gear). Modern switches and NICs have auto-detection—they sense activity and adapt, but explicit negotiation is preferred. If you misconfigure (force 1G full-duplex on one side, auto on the other), you get a duplex mismatch: one side thinks it’s full-duplex (can transmit and receive simultaneously), the other thinks half-duplex (CSMA/CD). Collisions occur, performance tanks.
Q5. What is flow control? PAUSE frames and PFC?
IEEE 802.3x PAUSE is a simple flow control mechanism: if a receiver’s buffer fills, it sends a PAUSE frame to the sender, causing the sender to stop transmitting for a duration specified in the frame. When the buffer drains, the sender resumes.
PFC (Priority Flow Control, 802.1Qbb) extends PAUSE to per-priority classes. Instead of pausing all traffic, PFC pauses traffic on a specific priority (0–7) while allowing other priorities to continue. This is essential in data centers to prevent congestion on high-priority traffic (storage, realtime) without starving low-priority traffic (management).
💡 Tip: Interviewers at hyperscalers (Google, Meta) love PFC questions because it’s critical for lossless Ethernet in data centers. Understand the tradeoff: PFC prevents drops (good for RDMAt) but can cause deadlock if misconfigured (A waits for B, B waits for A). The solution: lossless topology + deadlock prevention (via cyclic priority routing).
Q6. What are the Ethernet speeds from 10Mbps to 400GbE?
| Standard | Speed | Media | Distance |
|---|---|---|---|
| 802.3 (10Base-T) | 10 Mbps | Cat 3/5 UTP | 100m |
| 802.3u (100Base-TX) | 100 Mbps | Cat 5 UTP | 100m |
| 802.3z (1000Base-LX/SX) | 1 Gbps | Fiber, UTP Cat 5e | 100–500m (fiber) |
| 802.3ab (1000Base-T) | 1 Gbps | Cat 5e/6 UTP | 100m |
| 802.3an (10GBase-T) | Cat 6/6a UTP | 55–100m | |
| 802.3by (25GBase-T) | 25 Gbps | Cat 8 UTP | 30–100m |
| 802.3bj (100GBase-KR4/LR4) | 100 Gbps | Backplane, Fiber | 1m–10km |
| 802.3cd (200GBase-KR4) | 200 Gbps | Backplane | 1m |
| 802.3dk (400GBase-KR8) | 400 Gbps | Backplane | 1m |
📌 Note: Notice the trend: twisted pair (UTP) tops out at 25G because cross-talk limits. Beyond 25G, you need backplane (short, controlled impedance) or fiber. This is why data centers moved to 400GbE backplane (25G × 16 lanes or 50G × 8 lanes).
Q7. What is MDI vs MDI-X? When do you need a crossover cable?
MDI (Medium-Dependent Interface) uses Pin 1/2 for transmit, 3/6 for receive. MDI-X (crossover) swaps them. Two devices with the same pin assignment (e.g., both MDI) need a crossover cable to connect; otherwise, TX/RX lines don’t match.
In my experience, this is mostly legacy knowledge. Modern devices have auto-MDI-X (they detect which end is which and auto-swap internally). But if you’re connecting two 10-year-old managed switches without auto-MDI-X, you need a crossover cable. Newer standards (10GBase-T) enforce MDI-X on all devices, so crossover cables are obsolete.
Q8. What is FCS? Why 4 bytes?
FCS (Frame Check Sequence) is a 32-bit CRC computed over DA, SA, Type, and Payload using the polynomial 0x04C11DB7. It detects bit errors in transit. 32 bits provides good error detection for frames up to ~4000 bytes (probability of undetected error is ~10^-10).
The FCS is computed at TX (MAC appends it) and verified at RX. If the CRC doesn’t match, the frame is discarded. Note: PHY errors (preamble corruption, signal integrity) are caught earlier, before FCS check.
Q9. What is the minimum and maximum Ethernet frame size? Runt? Jumbo?
Minimum is 64 bytes (including FCS). Anything less is a runt frame (CRC error). Maximum standard is 1518 bytes (includes FCS). With 802.1Q VLAN tag, it’s 1522 bytes. A jumbo frame is any frame larger than 1518 bytes, up to 9000+ bytes (proprietary, vendor-specific). Jumbo frames improve throughput (fewer frames, less overhead) but require all devices to support them.
Q10. What is the Inter-Packet Gap (IPG)? Why 12 bytes?
IPG is the minimum idle time between frames. At 10 Mbps with a 96-bit (12-byte) gap, that’s 9.6 microseconds. Why 12 bytes? It’s historical (clock recovery time on old repeaters). Modern Ethernet doesn’t strictly require it, but it’s part of the spec. If you violate IPG (transmit frames back-to-back), some devices might misinterpret the boundary or drop frames.
💡 Tip: Modern MACs can transmit back-to-back with zero IPG if needed (called “tight packing”), but it’s not standard. Violations are usually silently tolerated. Interviewers rarely test IPG unless they’re from an embedded MAC team.
Section 2: PHY & MAC Architecture (Q11–Q20)
Q11. Where does Ethernet fit in the OSI model?
Ethernet is split between Layer 1 (Physical) and Layer 2 (Data Link). MAC (Media Access Control) is Layer 2 (framing, addressing, flow control). PHY (Physical Layer) is Layer 1 (electrical signals, encoding, synchronization). A typical device has a PHY chip connected to a MAC controller (or integrated on one die).
Q12. What are MII, GMII, XGMII interfaces? Compare them.
| Interface | Bus Width | Clock (MHz) | Data Rate | Standard |
|---|---|---|---|---|
| MII | 4 bits | 25 | 100 Mbps | 802.3u |
| GMII | 8 bits | 125 | 1 Gbps | 802.3z/ab |
| XGMII | 32 bits | 156.25 | 10 Gbps | 802.3ae |
| CGMII | 64 bits | 312.5 | 40 Gbps | 802.3ba |
Notice the pattern: bus width × clock frequency = data rate. MII is 4 bits × 25 MHz = 100 Mbps. GMII is 8 bits × 125 MHz = 1 Gbps. At 10G+, parallel buses become impractical (too many pins), so you switch to serial (SERDES).
Q13. What is SGMII? How does it use 8b/10b encoding?
SGMII (Serial Gigabit Media Independent Interface) serializes GMII onto a single differential pair, reducing pins from 20+ to 2. It uses 8b/10b encoding: 8 data bits become 10 transmitted bits, giving clock recovery data and DC balance. A 1.25 Gbps serial clock carries 1 Gbps of actual data (10/8 ratio).
Q14. What is the PCS (Physical Coding Sublayer)? What does it add?
PCS sits between MAC and PHY, handling encoding (8b/10b, 64b/66b), clock recovery, and frame synchronization. It ensures data is correctly encoded for transmission and decoded on receive. At 10G+, PCS is critical for signal integrity.
Q15. What is SERDES? What are CDR, PLL, and equalizer?
SERDES (Serializer/Deserializer) converts parallel data to serial (TX) and serial back to parallel (RX). Inside SERDES: CDR (Clock Data Recovery) extracts clock from the data stream, PLL (Phase-Locked Loop) synthesizes the recovered clock, Equalizer compensates for channel distortion (high-frequency loss, ISI).
Q16. What is 64b/66b encoding? Why not 8b/10b at 10G+?
64b/66b uses a 2-bit header + 64 data bits, achieving 97% efficiency vs 80% for 8b/10b. At 10G, 8b/10b requires 12.5 Gbps clock; 64b/66b needs only 10.3 Gbps, reducing power and enabling longer reaches. 64b/66b is used in 100GbE, 400GbE. The tradeoff: 64b/66b has weaker clock recovery (only 2-bit headers), requiring careful equalizer design.
Q17. What is an RGMII interface?
RGMII (Reduced Gigabit MII) reduces GMII pins by half (12 vs 24) by double-sampling data on both rising and falling edges. It runs at 125 MHz with 4-bit wide bus (same as MII) but achieves 1 Gbps via DDR. Used in consumer routers, switches.
Q18. What is the MAC RX path? (Preamble stripping, FCS check, IPG enforcement)
RX path: PHY delivers nibbles (4 bits at 25 MHz for 100M, 8 bits at 125 MHz for 1G) to MAC. Preamble/SFD detector waits for 7-byte preamble + SFD, then signals frame start. Frame assembly collects DA, SA, Type, Payload into a buffer. FCS check compares received CRC with computed CRC; bad frames are dropped. Length check verifies frame is not a runt or oversized. IPG enforcement (optional) waits for 12-byte gap before accepting next frame.
Q19. What is the MAC TX path? (Preamble/SFD insertion, FCS generation, padding)
TX path: Application provides DA, SA, Type, Payload to MAC buffer. Preamble/SFD insertion prepends 7-byte preamble + SFD. Padding adds zeros if payload < 46 bytes (to meet minimum 64-byte frame). FCS generation computes CRC over DA–Payload and appends 4-byte CRC. PHY delivers the bit stream to the line.
Q20. What is MDIO? How do you read/write PHY registers?
MDIO (Management Data Input/Output) is a low-speed serial interface (2 pins: clock, data) for the MAC to read/write PHY registers. Standard sequence: MAC outputs a Start-Of-Frame (SoF), clause (C22 or C45), operation (read/write), PHY address (5 bits), register address (5 bits), turnaround, data (16 bits). The register may define speed, duplex, auto-negotiation status, or link state.
📌 Note: MDIO is slow (typical 1–20 MHz) and exists on almost every Ethernet NIC. Most of the initialization (auto-neg, link detect) happens via MDIO read/write. Interviewers expect you to know it exists and that MAC and PHY are separate (logically, though often integrated).
Section 3: 10G+ Ethernet (Q21–Q30)
Q21. What are XAUI, XFI, SFI? What’s the difference?
XAUI (10G Attachment Unit Interface) is a 4-lane parallel interface, each lane 3.125 Gbps (4 × 3.125 = 12.5 Gbps on the wire, or 10 Gbps effective after 8b/10b). XFI (10G Fabric Interface) is a single-lane serial equivalent (3.125 Gbps). SFI (Serdes Framer Interface) is similar to XFI but includes the framing/serialization layer. In practice, XAUI is older (used in early 10GbE NICs), XFI/SFI are modern (used in recent Broadcom, Mellanox chips).
Q22. Why is 25GbE 25G? How is it related to 100G (4×25G)?
25GbE emerged from 100G port disaggregation. A 100G link can be split into four 25G lanes (or two 50G). This flexibility allows vendors to build modular systems: 25G for edge, aggregated to 100G/400G in the spine. 25GbE is becoming the standard building block (like how 10G was for the previous decade).
Q23. How do 40GbE (4×10G XLAUI) and 100GbE (4×25G CAUI-4) compare?
Both use 4 lanes, but 40GbE runs each lane at 10.3 Gbps (via 8b/10b), while 100GbE runs at 25.78 Gbps (via 64b/66b). 100GbE is more power-efficient (fewer transceivers, better encoding). 40GbE is largely obsolete (existed 2008–2012); most systems jumped from 10G directly to 100G.
Q24. What are the 400GbE architecture options?
400GbE can be: 8×50G (used in some backplane designs), 4×100G (most common), 2×200G (emerging, PAM-4 based). Each lane uses different modulation (PAM-4 for 50/100/200G, QPSK/PAM-4 mix for others). The tradeoff: more lanes = more power, fewer lanes = higher per-lane speed (harder to implement).
Q25. What is RS-FEC (Reed-Solomon Forward Error Correction)? Which clause requires it?
RS-FEC adds redundancy (overhead ~7%) to correct burst errors on lossy channels. At 25G, the BER (Bit Error Rate) gets high enough (~10^-6) that FEC is mandatory; without it, you’d see unacceptable frame loss. IEEE 802.3by (25GBase-T) mandates RS-FEC. IEEE 802.3bj (100GbE) and above also require it. The benefit: allows longer reach (100m on 25GBase-T) that wouldn’t be possible without FEC.
Q26. What is KR/KR4 backplane Ethernet?
KR (Clause 72) defines electrical backplane Ethernet: a single differential pair, AC-coupled, using SERDES with receiver equalization. KR4 is 4-lane (100GbE backplane at 25.78 Gbps per lane). The advantage: backplane is passive (no active components), so reach is 1–2 meters, and cost is low. Used in hyperscale datacenters (Google, AWS) for top-of-rack to spine connections.
Q27. What is TSN (Time-Sensitive Networking)?
TSN is a suite of IEEE 802.1 standards for deterministic, low-latency Ethernet. Key standards: 802.1Qbv (credit-based scheduler for time-critical traffic), 802.1AS (gPTP, precision time sync), 802.1CB (frame replication/elimination for reliability). Used in industrial automation, automotive, real-time control.
Q28. What is MACsec (IEEE 802.1AE)? How does it encrypt Ethernet at line rate?
MACsec encrypts and authenticates Ethernet frames in hardware (between PHY and MAC), adding a SecTAG header and ICV (Integrity Check Value). It operates at line rate (no software overhead). All modern 10G+ NICs support it. Tradeoff: 16-byte overhead per frame, adds latency (encryption), but provides strong security without app-level changes.
Q29. What is RDMA over Converged Ethernet (RoCE)?
RoCE (RDMA over Converged Ethernet) allows remote memory access directly from hardware, bypassing the OS kernel. It requires lossless Ethernet (via PFC + ECN), low latency, and high bandwidth. RoCE v2 runs over UDP/IP, making it more flexible than v1. Used in data centers for storage (NVMe-oF), HPC, and big-data workloads where latency matters.
Q30. What is Ethernet in automotive? 100BASE-T1 and 1000BASE-T1?
Automotive Ethernet uses single twisted pair (instead of two in twisted pair) to reduce weight/cost. 100BASE-T1 (100 Mbps) is standardized for in-vehicle networks. 1000BASE-T1 (1 Gbps) is emerging for autonomous vehicles (camera/sensor aggregation). Both use PAM-3 modulation (three voltage levels) and include galvanic isolation for EMI robustness. OPEN Alliance (automotive OEM group) standardizes these.
Section 4: Design & Verification (Q31–Q40)
Q31. What is the Ethernet MAC RTL design? TX and RX state machines?
TX state machine: IDLE → wait for application data → PREAMBLE → insert SFD → PAYLOAD → accumulate data in FIFO → FCS → append CRC, pad if needed → TRANSMIT → serialize to PHY. RX state machine: IDLE → DETECT_PREAMBLE → check for SFD → COLLECT_FRAME → accumulate DA, SA, Type, Payload → CHECK_FCS → if good, signal application with frame length and data.
Q32. How big does the TX FIFO need to be for Ethernet?
Minimum: one complete frame (1518 bytes). Better: 2–4 frames (3–6KB) to avoid underrun if the application is slow to refill. At 100 Mbps, one frame takes ~120 microseconds; if the application stalls for longer, the PHY will run out of data, causing a runt frame. FIFO sizing is a trade-off: larger FIFO hides application latency but costs silicon and power.
Q33. What is PTP (IEEE 1588)? Transparent clock vs boundary clock?
PTP (Precision Time Protocol) synchronizes clocks across a network with sub-microsecond accuracy. A transparent clock measures the residence time of a packet and adjusts the timestamp en route (hardware-based, no packet modification). A boundary clock re-times the packet using its own clock (creates a new timeline, useful for bridging isolated networks). Used in finance (HFT), power grids, telco, where timing is critical.
Q34. What is TCAM for MAC address lookup?
TCAM (Ternary Content-Addressable Memory) allows parallel lookup of MAC addresses in O(1) time. A MAC forwarding table is stored in TCAM; on a frame arrival, you query the DA, and TCAM returns the port immediately (vs a tree search which is O(log N)). Each TCAM entry is 48 bits (MAC) + mask bits (wildcards) + result (port). Switches use TCAM extensively; it’s power-hungry but fast.
Q35. What is Ethernet switch architecture? Cut-through vs store-and-forward?
Store-and-forward buffers the entire frame before forwarding. Advantage: frame is validated (FCS checked) before egress; bad frames don’t consume uplink bandwidth. Disadvantage: high latency (one full frame time). Cut-through forwards the frame as soon as DA is available (before RX completes). Advantage: low latency. Disadvantage: bad frames are still forwarded (wasting bandwidth). Modern switches use cut-through by default (latency matters) with FCS error suppression (drop bad frames after forwarding).
Q36. What is a DMA engine for Ethernet?
DMA (Direct Memory Access) engine transfers data between NIC and system memory without CPU intervention. Descriptor ring is a circular buffer where the driver posts DMA instructions (read/write address, length). The DMA engine processes descriptors in sequence, transferring data. Scatter-gather allows one DMA operation to write to multiple memory locations (useful for assembling packets from buffer pools). Most modern Ethernet NICs have DMA engines for high-speed operation.
Q37. What are the top 5 common Ethernet MAC bugs?
| Bug | Symptom | Fix |
|---|---|---|
| FCS Corruption | Good frames dropped, bad CRC errors | Check CRC polynomial, seed init |
| Preamble Stripping | Frames misaligned, DA shifted | Debug preamble detector FSM |
| CDC Metastability | Rare frame loss, link drop | Add synchronizers on clock domain crossings |
| FIFO Overflow | Frame loss under load, CRC errors | Increase FIFO depth, tune scheduler |
| Padding Logic | Short frames garbled, length wrong | Check 46-byte minimum, padding logic |
Q38. What is the Ethernet verification strategy?
Key test cases: Basic sanity (send frame, receive it intact), boundary conditions (minimum 64B, maximum 1518B frames, runt frames), FCS validation (corrupt one bit, check frame is dropped), back-to-back frames (zero IPG), pause frames (send PAUSE, verify no TX), long stress (run for hours, check for bit errors or deadlock), MDIO operations (read/write PHY registers), link state changes (plug/unplug, check for glitches). Integration testing includes real chips and loopback cables.
Q39. What is VLAN tagging (802.1Q)? How does it extend the frame?
VLAN (Virtual LAN) tag is inserted after the SA field, before the Type field. It’s 4 bytes: 16-bit TPID (0x8100), 3-bit priority (0–7), 1-bit CFI (canonical format), 12-bit VLAN ID (VID, 1–4094). A VLAN-tagged frame is 1522 bytes (vs 1518 untagged). Switches use VID to forward frames (each port is assigned one or more VLANs), providing isolation and broadcast containment.
Q40. Where are the clock domain crossings in an Ethernet MAC?
CDC (Clock Domain Crossing) occurs at: PHY clock (125 MHz for 1G) to MAC clock (100–200 MHz) — need synchronizers on TX_CLK and RX_CLK. Application clock to MAC clock** — data and control signals. Reset domain — async reset from outside. Missing synchronizers cause metastability: setup/hold violations that manifest as rare frame corruption or link flaps. Proper CDC design (use proper synchronizer cells, 2–3 flops minimum) is essential for reliability.
📌 Note: CDC bugs are the most insidious Ethernet MAC bugs. They’re hard to reproduce and debug (happen randomly in simulation, reliably only on silicon under temperature/voltage variation). Good interview answer: identify all clock domains, explain why each needs a synchronizer, and propose solutions (Gray counters, handshakes, dual-clock FIFOs).
Most-Asked Topics by Company
| Company | Focus Areas |
|---|---|
| Broadcom, Marvell, Cavium | PHY design, SerDes, FEC, 25G+ speeds |
| Intel, Xilinx | MAC/PHY integration, FPGA implementation, KR backplane |
| Cisco, Arista, Juniper | Switch design, PFC, TSN, high-density ports |
| Google, Meta, AWS | Custom MAC, power/perf, RoCE, 400GbE, open standards |
| Mellanox (NVIDIA), Solarflare | Low-latency NIC, RoCE, hardware offload |
Resources & Further Reading
- IEEE Standards: 802.3 (base), 802.3ab (1GbE), 802.3an (10GbE), 802.3bj (100GbE), 802.3dk (400GbE)
- Reference Books: “Ethernet the Definitive Guide” (Spurgeon), “High-Speed Digital Design” (Johnson/Graham)
- Tools: PADS, Cadence, Synopsys for MAC/PHY design; Wireshark for frame analysis
- Validation: Ixia (now Keysight), Spirent for traffic generation and frame analysis
- Interview Prep: Draw block diagrams, understand timing (setup/hold for CDC), practice frame format questions
Last updated: 2026. Ethernet is a mature standard, but high-speed variants (25G, 100G, 400G) are still evolving. Focus on understanding the why behind standards, not just memorizing specs.
