The short answer: SystemVerilog interviews usually have two halves. For design roles: logic vs wire, always_comb and always_ff, unique and priority, structs, enums and interfaces. For verification roles: classes and OOP, randomisation and constraints, arrays and queues, mailboxes and fork-join, functional coverage and assertions (SVA). Know both halves at a basic level, and go deep on the half that matches the job.
SystemVerilog is really two languages in one: a better Verilog for writing RTL, and an object-oriented language for building testbenches. Interviewers know this, so the questions you get depend a lot on the role.
I’ve split this post the same way. If you’re interviewing for verification, also read my design verification interview questions, which cover methodology and UVM.
- SystemVerilog for design
- Classes and OOP
- Randomisation and constraints
- Testbench mechanics
- Coverage and assertions
Table of Contents
Part 1: SystemVerilog for design
1. What is the difference between logic, wire and reg?
logic is a 4-state type that can be assigned from a procedural block or a continuous assign, so it replaces reg and most wires. The catch: a logic variable can have only one driver. If a signal has multiple drivers, such as a tri-state bus, it must be a net like wire.
2. What is the difference between 2-state and 4-state types?
4-state types (logic, integer) hold 0, 1, x and z and start as x. 2-state types (bit, byte, int, longint) hold only 0 and 1 and start as 0. 2-state types simulate faster and are fine for testbench counters, but in RTL they can hide x bugs, such as a missing reset.
3. Why use always_comb instead of always @(*)?
- It runs once at time zero, so outputs are correct before any input changes.
- It’s sensitive to signals read inside functions it calls.
- Tools warn you if it infers a latch, and it forbids other blocks from driving the same variables.
always_ff and always_latch do the same for flops and latches: they state your intent, and tools check it.
4. What do unique and priority mean on a case statement?
unique says exactly one item will match, so the items can be evaluated in parallel; the simulator warns if none or more than one match. priority says the first match wins and at least one will match. Both replace the dangerous full_case/parallel_case synthesis pragmas with checks you can see in simulation.
5. What is the difference between packed and unpacked arrays?
A packed array is one contiguous vector, like logic [3:0][7:0] word, so you can slice it and do arithmetic on it. An unpacked array, like logic [7:0] mem [0:255], is a collection of separate elements, used for memories and lists.
6. Why use enums for FSM states?
typedef enum logic [1:0] {IDLE, REQ, WAIT, DONE} state_t;
state_t state, next;Waveform viewers show state names instead of numbers, the compiler checks assignments, and you can still choose the encoding.
7. What are interfaces and modports?
An interface bundles related signals (say, an AXI or APB bus) into one object you connect with one port. Modports define the direction of each signal from a given side, such as master or slave. Interfaces can also hold tasks, assertions and clocking blocks.
8. Package or `include?
Packages are the right way to share types, parameters and functions: they have their own namespace and are compiled once. `include just pastes text, which leads to duplicate definitions if a file is included twice.
Part 2: Classes and OOP
9. What is the difference between a class and a struct?
A struct is a value: copying it copies the data, and it can be used in synthesisable RTL. A class is a dynamic object reached through a handle; it supports inheritance, virtual methods and randomisation, but only in testbenches.
10. What is a handle, and what is the difference between a shallow and a deep copy?
A handle is a reference to a class object; assigning one handle to another makes both point to the same object. b = new a; makes a shallow copy: a new object with copies of a’s fields, but any objects a points to are shared. A deep copy also copies those inner objects, which you write yourself (usually as a copy() method).
11. What are virtual methods and polymorphism?
class base;
virtual function void show(); $display("base"); endfunction
endclass
class child extends base;
function void show(); $display("child"); endfunction
endclass
base b; child c = new;
b = c;
b.show(); // prints "child" because show() is virtualWithout virtual, the call would follow the handle type and print “base”. Polymorphism is what lets UVM call your overridden methods through base-class handles.
12. What is an abstract class?
A class declared with virtual class. You can’t create an object of it; it exists to be extended. It can declare pure virtual methods that every child must implement.
13. What does static mean on a class member?
A static property is shared by all objects of the class, such as a counter of how many packets were created. A static method can be called without an object, but can only access static members.
Part 3: Randomisation and constraints
14. What is the difference between rand and randc?
rand picks a value randomly each time, so repeats are possible. randc cycles through every possible value in a random order before repeating any, like dealing a shuffled deck. randc is expensive for wide variables, so use it on small ones.
15. Write a class with a few useful constraints.
class packet;
rand bit [7:0] len;
rand bit [7:0] data[];
rand bit [3:0] kind;
constraint c_len { len inside {[4:64]}; }
constraint c_size { data.size() == len; }
constraint c_dist { len dist { [4:15] := 3, [16:64] :/ 2 }; }
constraint c_kind { soft kind == 0; }
endclass:= gives the weight to every value in the range; :/ splits the weight across the range. A soft constraint can be overridden by a later inline constraint without causing a failure.
16. How do you generate an array of unique values?
rand bit [7:0] arr[10];
constraint c_unique { unique {arr}; }Without the unique keyword: foreach (arr[i]) foreach (arr[j]) if (i != j) arr[i] != arr[j];
17. What does solve…before do?
It changes the probability distribution, not the set of legal solutions. For example, with a constraint linking a mode bit to a length, solve mode before len; makes each mode equally likely instead of being swamped by the many legal lengths of one mode.
18. What are pre_randomize and post_randomize?
Callbacks that run automatically before and after randomize(). I use post_randomize to compute derived fields, like a checksum over randomised data.
19. How do you add a constraint for one call only?
assert(pkt.randomize() with { len == 16; });Always check the return value: randomize() returns 0 when constraints conflict, and silently using the old values is a common bug.
Part 4: Testbench mechanics
20. Dynamic array, queue or associative array?
Dynamic array when you know the size at run time (a packet payload). Queue when items come and go at the ends (a scoreboard’s expected list). Associative array for sparse data with any key type (a memory model with a few written addresses).
21. What is a virtual interface, and why do we need it?
Interfaces are static and are created at elaboration; class objects are dynamic and are created at run time. A class can’t contain an interface instance, so it holds a virtual interface: a handle pointing to a real interface instance in the testbench top. In UVM you pass it through uvm_config_db.
22. What is a clocking block for?
It defines when the testbench samples inputs and drives outputs relative to a clock, with input and output skews. That removes races between the testbench and the DUT, which is the main reason it exists.
23. fork-join vs join_any vs join_none?
join waits for all threads; join_any waits for the first one; join_none doesn’t wait at all. After join_any, the other threads keep running, so use disable fork if you want to stop them, and wait fork to wait for all child threads.
24. Mailbox, semaphore or event?
A mailbox passes data between threads, like a FIFO (generator to driver). A semaphore controls access to a shared resource with keys. An event is a pure synchronisation signal with no data.
Part 5: Coverage and assertions
25. What is the difference between code coverage and functional coverage?
Code coverage is automatic and tells you which lines, branches, toggles and FSM states were exercised. Functional coverage is written by you, from the spec, and tells you which features and scenarios were tested. 100% code coverage with poor functional coverage still means untested features.
26. Write a covergroup with bins and a cross.
covergroup cg @(posedge clk);
cp_len : coverpoint len {
bins small = {[4:15]};
bins medium = {[16:47]};
bins large = {[48:64]};
}
cp_kind : coverpoint kind { bins k[] = {[0:3]}; }
x_len_kind : cross cp_len, cp_kind;
endgroup27. Immediate vs concurrent assertions?
An immediate assertion checks a condition at one point in procedural code, like an if. A concurrent assertion is clocked and checks behaviour over time, using sequences and properties. Concurrent assertions are what people mean by SVA.
28. What is the difference between |-> and |=>?
Both are implication: if the left side matches, check the right side. |-> starts checking the right side in the same cycle the left side ends; |=> starts in the next cycle. So a |=> b is the same as a |-> ##1 b.
29. Write an assertion: every request gets an acknowledge within 1 to 3 cycles.
property p_req_ack;
@(posedge clk) disable iff (!rst_n)
req |-> ##[1:3] ack;
endproperty
a_req_ack: assert property (p_req_ack)
else $error("ack not seen within 3 cycles of req");30. What do $rose, $fell, $stable and $past do?
$rose(sig) is true when sig went from 0 to 1 between the previous and current clock; $fell is the opposite; $stable means it didn’t change; $past(sig, n) returns its value n cycles ago. They let you write edge-based checks without extra flops.
Practise this on VLSI Forge
I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.
FAQ
Do I need UVM for a SystemVerilog interview?
For verification roles, usually yes, at least the basics. For design roles, no; focus on the design features in Part 1.
Which topics come up most?
Classes and polymorphism, randomisation and constraints, and SVA implication operators. Practise writing constraints and assertions by hand.
Is the program block still used?
It was meant to avoid testbench-DUT races, but most modern UVM testbenches use modules and clocking blocks instead. Know what it does, but you rarely need it.
What is the best book for SystemVerilog verification?
SystemVerilog for Verification by Chris Spear and Greg Tumbush is the usual starting point.
