Browsing: Logic design

Verilog

Tasks and Functions in Verilog: Differences, Arguments and Examples

Raju Gorla31 July 2026

Verilog tasks vs functions explained with examples: return values, timing controls, synthesis, how arguments are passed, and static vs automatic.

Verilog

Blocking vs Non-Blocking Assignments in Verilog (with Waveforms)

Raju Gorla25 July 2026

Blocking (=) vs non-blocking (<=) assignments explained with waveforms, the Verilog scheduling regions behind them, race conditions, and the rules to follow in RTL.

Verilog

Verilog Syntax Basics: Comments, Identifiers and Number Formats

Raju Gorla18 July 2026

Verilog’s basic syntax rules in one place: comments, identifiers, keywords, sized and unsized numbers, x and z values, strings and the mistakes beginners make most.