The Verilog system tasks I actually use: $display vs $strobe vs $monitor, format specifiers, $finish, file I/O, $readmemh, waveform dumping, $random and $clog2.
Browsing: SystemVerilog
SystemVerilog assertions explained with a waveform: immediate vs concurrent, implication, sequences, $rose, $stable and $past, assert vs assume vs cover, formal verification and assertions worth adding to every design.
SystemVerilog data types explained: logic vs bit, 2-state and 4-state types, enums, packed structs and unions, packed vs unpacked arrays, dynamic arrays, queues and associative arrays.
What UVM is, why it exists, its core classes, a minimal UVM test, and a learning path through my UVM series.