Samsung Interview Experience (FPGA Engineer Role)

I recently interviewed for an FPGA Engineer position at Samsung Research and Development (SRI-B) for a role requiring 2+ years of experience. Below is a structured breakdown of my interview process:

Round 1: Technical Interview (Online, ~1 Hour)

This round focused on work experience, FPGA fundamentals, and project discussions.

General & Project Discussion

1. Can you walk us through your work experience?

2. Explain your project data path using Paint/Paper.

Memory & DDR4 Experience

3. What did you work on DDR4? (Based on Resume)

4. What interface did you use for the DDR controller?

5. How did you configure the EMIF (DDR controller)?

OFDM IP (Based on Resume)

6. Explain the OFDM IP you worked on.

7. Draw the Interfaces & FSMs you built for OFDM.

8. Discuss the FSM design considerations for your implementation.

9. What interfaces did you use for OFDM?

10. How did you handle AXI4-Stream in OFDM?

AXI Protocols & FPGA Design

11. Explain AXI4 vs AXI4-Lite.

12. Describe your experience with timing analysis & constraints.

13. How did you resolve CDC (Clock Domain Crossing) issues?

14. Explain False Paths & Multi-cycle Paths.

Software, Verification & Debugging

15. Do you have experience with scripting languages?

16. How would you rate yourself in C programming?

17. Have you written C drivers for IPs?

18. How do you generate data to verify your IPs (like OFDM)?

19. Explain the complete FPGA design flow.

20. Describe your Vitis experience.

Final Discussion

21. The interviewer explained Samsung’s role and requirements, and we discussed my fit for the position.

Round 2: Technical & System-Level Discussion (Onsite, ~50 Min)

This round focused on a deeper system-level understanding of FPGA workflows.

Samsung’s Requirements & Project Overview

1. The interviewer explained their projects and expectations.

2. Can you provide a system-level view of your current project?

FPGA & Software Flows

3. Explain the Vivado flow (from design entry to bitstream generation).

4. How does Vitis flow work for software emulation?

5. What is the flow for validating on FPGA boards?

Hardware & Software Integration

6. Have you written C drivers for IPs?

7. What automation and scripting languages have you used?

Ethernet & DDR Experience

8. Since you worked on Ethernet IPs, can you explain the Ethernet interfaces you handled?

9. What have you worked on regarding DDR controllers?

RTL Development & System Simulations

10. How much RTL coding have you done in the past two years?

11. Explain the FSM interfaces you built for OFDM.

12. What experience do you have with QEMU simulations?

Samsung IPs & Role Interest

13. The interviewer discussed Samsung’s ISP, Video IPs, and other Samsung IPs.

14. Are you interested in this role?

Round 3: Final Interview (Onsite, ~40 Min)

This round was a mix of technical, experience-based, and cultural-fit discussions.

Self-Introduction & Project Discussion

1. Can you introduce yourself and explain your projects?

2. Why do you want to leave your current company?

Work Experience & FPGA Preferences

3. Which FPGAs have you worked on so far?

4. Since you used both Xilinx and Altera FPGAs, which one do you prefer?

5. Explain your project data path in detail.

6. What were the resource utilization numbers in your current project?

7. Have you worked on optimization techniques for congestion?

Timing & Software Integration

8. What is your experience with Timing Analysis and SDC?

9. Have you worked on SW flow along with FPGA flow?

QEMU & Virtualization

10. What is QEMU, and what have you worked on in that area?

Samsung Work Culture & Teams

11. The interviewer explained Samsung’s teams, products, and work environment.

Final Thoughts

The interview process was technically intensive, covering:
✅ FPGA design, verification, interfaces, timing analysis, software integration, and scripting.
✅ System-level integration, debugging techniques, and workflow automation.
✅ Hardware/software co-design, DDR, and AXI protocols.

The experience was insightful, and the discussions about system validation, RTL coding, and FPGA workflows were particularly engaging.

Hope this helps anyone preparing for a similar role!