The short answer: a physical design (PD) engineer takes the gate-level netlist produced by synthesis and turns it into a real layout: where every cell sits, how the clock reaches every flop, and how millions of wires are routed. The goal is a layout that meets timing, power and area targets and passes every manufacturing check, ready for tape-out.
Physical design is where a chip stops being code and becomes geometry. It is a big employer in India, especially at design service companies, and it suits people who like optimisation puzzles where every fix affects something else. Here is what the work is really like.
- What a physical design engineer actually does
- A typical week
- The skills you need
- Tools you will use
- How I would get started
- Where the role leads
Table of Contents
Part 1: What a physical design engineer actually does
A PD engineer usually owns a block, or part of a large block. You start with the netlist and constraints, plan the floorplan (where big macros and memories go), build the power grid, place the standard cells, build the clock tree, route the wires, and then iterate until timing, congestion, power and physical checks are all clean.
Much of the job is trade-offs. Moving a macro might fix congestion but break timing. Upsizing cells might fix timing but raise power and IR drop. Good PD engineers understand why each fix works and what it costs.
Part 2: A typical week
A typical week in PD looks something like this:
- Running or re-running a block through placement, CTS and routing
- Analysing timing reports and fixing violating paths
- Fixing congestion hotspots by adjusting the floorplan or placement
- Checking IR drop and electromigration on the power grid
- Cleaning up DRC and LVS issues before sign-off
- Writing Tcl scripts to automate steps and generate reports
Part 3: The skills you need
In my view, the most important PD skill is reading reports well. The tools produce huge timing, congestion and power reports, and the engineer who can quickly spot the real problem among thousands of lines is the one who closes the block on time.
Scripting is the other big one. Almost every PD tool is driven by Tcl, and a good script that sets up runs or summarises reports can save your whole team hours every week.
Part 4: Tools you will use
At work you will use a place-and-route tool such as Cadence Innovus or Synopsys IC Compiler II and Fusion Compiler, timing tools like PrimeTime or Tempus, power and IR tools like RedHawk or Voltus, and physical verification tools like Calibre for DRC and LVS. To learn at home, OpenROAD and OpenLane with an open PDK such as SKY130 let you run a full flow for free.
Part 5: How I would get started
- Learn digital fundamentals and STA basics: setup, hold, skew, clock trees.
- Understand CMOS, standard cells and why layout design rules exist.
- Run a small design through OpenLane or OpenROAD with an open PDK, from RTL to GDS.
- Learn Tcl well enough to write small scripts for the tools.
- Practise explaining the PnR flow and common fixes for timing and congestion, as interviewers ask about them often.
Practise this on VLSI Forge
I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.
Physical Design problems · Static Timing Analysis problems · Physical Design Closure course
Part 6: Where the role leads
PD engineers grow from running blocks, to owning difficult blocks, to leading the physical implementation of a whole chip (often called a full-chip or top-level PD lead). Senior engineers often specialise in areas like clock design, power integrity, or methodology and flow development.
PD is also a natural base for STA, and some PD engineers move into EDA companies as application engineers or tool developers.
FAQ
Is physical design a good career for freshers?
Yes. It is one of the largest VLSI employers in India, especially at service companies, and good PD engineers are always in demand.
Do PD engineers write RTL?
No, not usually. They work with the netlist. But understanding RTL helps when you need to talk to designers about timing problems.
How important is Tcl for PD?
Very. Almost every PD tool is controlled through Tcl. You do not need to be a programmer, but you should be comfortable writing scripts.
Is PD affected by advanced nodes?
A lot. New nodes bring new rules, more variation and new structures like backside power delivery, which is why experienced PD engineers stay in demand.
