The short answer: for VLSI interviews, the computer architecture topics that come up most are the 5-stage pipeline and its hazards (data, control and structural), forwarding and stalls, caches (mapping, write policies, miss types), memory hierarchy and virtual memory basics, branch prediction, and, for senior roles, out-of-order execution and cache coherence. Being able to explain them with a simple diagram matters more than memorising definitions.
Even if you are applying for a verification or physical design role, interviewers like to ask architecture questions, because they show how well you understand the hardware you will be working on. Here are the topics I would prepare, and how deep to go for each.
- The 5-stage pipeline
- Hazards, forwarding and stalls
- Caches and memory hierarchy
- Branch prediction and beyond
- How I would prepare
Table of Contents
Part 1: The 5-stage pipeline
Be ready to draw it and explain what each stage does, why pipelining improves throughput but not the latency of a single instruction, and what the pipeline registers between stages hold.
Part 2: Hazards, forwarding and stalls
- Data hazards: an instruction needs a result that is not written back yet. Know how forwarding fixes most of them, and why a load followed by a use still needs one stall.
- Control hazards: branches change the PC. Know flushing, branch delay and why prediction helps.
- Structural hazards: two instructions need the same hardware in the same cycle.
Part 3: Caches and memory hierarchy
- Direct-mapped, set-associative and fully associative caches, and how an address splits into tag, index and offset.
- Write-through vs write-back, and write-allocate vs no-write-allocate.
- The three Cs of misses: compulsory, capacity and conflict.
- Replacement policies such as LRU, and why true LRU is expensive in hardware.
- Basic virtual memory: pages, page tables and the TLB.
Part 4: Branch prediction and beyond
- Static prediction vs simple dynamic predictors like a 2-bit saturating counter.
- Branch target buffers.
- For senior roles: out-of-order execution, register renaming, reorder buffers, and cache coherence protocols like MESI.
Part 5: How I would prepare
- Read Patterson and Hennessy (RISC-V edition) chapters on pipelining and memory.
- Build a simple pipelined CPU in Verilog. Nothing makes hazards clearer than debugging your own forwarding logic.
- Practise drawing pipeline diagrams for short instruction sequences, with stalls and forwarding marked.
- Work out cache address splits for a few example configurations by hand.
Practise this on VLSI Forge
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Build a RISC-V CPU step by step · RTL Design problems
FAQ
Do verification engineers get architecture questions?
Yes, often. Verifying a CPU, cache or interconnect is much easier if you understand how it works, so interviewers check that.
How deep do I need to go as a fresher?
Pipelining, hazards, forwarding and cache basics are usually enough. Out-of-order execution and coherence are more common for experienced roles.
Which ISA should I learn?
RISC-V. It is simple, open, widely taught, and used in many real chips and interview questions.
Is building a CPU really worth it?
Yes. A pipelined RISC-V core you built and debugged yourself is one of the strongest things you can bring to an interview.
