Browsing: System Verilog

System Verilog

SystemVerilog for RTL Design: always_ff, always_comb, Packages and More

Raju Gorla6 July 2026

The SystemVerilog features I use in synthesisable RTL: always_ff and always_comb, unique and priority, packages, enums and structs, and what synthesis does with each.

System Verilog

SystemVerilog Data Types: logic, enums, structs, queues and Associative Arrays

Raju Gorla5 July 2026

SystemVerilog data types explained: logic vs bit, 2-state and 4-state types, enums, packed structs and unions, packed vs unpacked arrays, dynamic arrays, queues and associative arrays.

System Verilog

What Is SystemVerilog? Features for Design and Verification

Raju Gorla4 July 2026

What SystemVerilog is, how it extends Verilog for RTL design and verification, a short history, what each role needs to learn, and a learning path.