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Informative

AI in Chip Design: What It Means for VLSI Engineers

Raju GorlaBy Raju Gorla5 October 2026Updated:11 October 2026No Comments4 Mins Read
AI in chip design: what it means for VLSI engineers
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The short answer: AI touches chip design in two ways. First, AI is now built into EDA tools, tuning synthesis and place-and-route settings, speeding up verification and helping engineers write RTL, scripts and documentation. Second, AI is the biggest reason new chips are being designed at all: GPUs, NPUs and custom accelerators. For engineers, that means learning to use AI tools well, checking their output carefully, and considering roles in AI hardware.

This page used to be two separate posts, one on VLSI design for AI and one on ChipGPT-style tools. I have merged them, because they are really two sides of the same story. Here is where things stand, without the hype in either direction.

  1. Two sides of AI and chips
  2. AI inside the design tools
  3. LLMs and “ChipGPT”-style assistants
  4. Chips for AI
  5. What this means for your career

Table of Contents

  • Part 1: Two sides of AI and chips
  • Part 2: AI inside the design tools
  • Part 3: LLMs and “ChipGPT”-style assistants
  • Part 4: Chips for AI
  • Part 5: What this means for your career
  • FAQ
    • Will AI replace VLSI engineers?
    • Can ChatGPT or other LLMs write Verilog?
    • What is the difference between a GPU and an NPU?
    • How do I get into AI hardware?

Part 1: Two sides of AI and chips

Two sides of AI and chips: AI for chip design, and chips for AI
AI changes both how chips are designed and which chips get designed.

Part 2: AI inside the design tools

Where AI already helps in the chip design flow
Assistants and optimisers, not replacements.

The big EDA vendors now ship AI features across the flow. Synopsys groups its work under Synopsys.ai, with tools that explore design settings automatically to improve power, performance and area, and to speed up verification and test. Cadence has Cerebrus for implementation optimisation, Verisium for verification and its JedAI data platform. Both have also added LLM-based assistants and, more recently, agent-style features that can carry out multi-step tasks.

In practice, these tools are best at searching huge option spaces faster than a person could, and at summarising and triaging large amounts of data. They still need engineers to set goals, judge results and sign off.

Part 3: LLMs and “ChipGPT”-style assistants

Large language models can now draft Verilog, testbenches, assertions and Tcl scripts. Research projects and benchmarks over the last few years have shown they can write correct code for small, well-specified blocks, and that they still make subtle mistakes on anything larger: off-by-one counters, missing reset handling, latches and CDC issues.

My advice is simple: use them like a fast, eager intern. Let them draft, then review, simulate and check everything yourself. Never paste generated RTL into a real design without understanding every line.

Part 4: Chips for AI

AI workloads are driving huge demand for new silicon: GPUs, NPUs in phones and laptops, and custom accelerators built by cloud and AI companies. Under the hood these chips are built from familiar pieces, multiply-accumulate (MAC) arrays, on-chip SRAM, high-bandwidth memory (HBM) interfaces and fast interconnects, often packaged as several chiplets. That means demand for RTL, verification, physical design and packaging engineers who understand how these accelerators work.

  • Learn how matrix multiplication maps to a systolic array.
  • Understand INT8 and other low-precision datapaths, and why they save power.
  • Learn the basics of memory bandwidth, because it often limits AI chips more than compute does.

Part 5: What this means for your career

  • Learn to use AI tools well. They will be part of your daily work, so get comfortable with them early.
  • Get even better at fundamentals. Checking AI output needs a deep understanding of timing, CDC and verification.
  • Consider AI hardware. It is one of the fastest-growing areas for design, verification and physical design roles.
  • Do not panic about replacement. AI is making engineers more productive. The people who know how to use it, and how to check it, will be the most in demand.

Practise this on VLSI Forge

I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.

Build an NPU step by step · RTL Design problems

FAQ

Will AI replace VLSI engineers?

Not any time soon. AI is automating parts of the work and making engineers faster, but someone still has to understand the design, judge results and sign off the chip.

Can ChatGPT or other LLMs write Verilog?

Yes, for small and well-specified blocks. They still make subtle mistakes, so every line must be reviewed and simulated.

What is the difference between a GPU and an NPU?

A GPU is a general parallel processor that is very good at AI. An NPU is specialised for neural network maths, usually trading flexibility for efficiency.

How do I get into AI hardware?

Learn the basics of MAC arrays, systolic arrays and low-precision arithmetic, build a small accelerator project, and look at roles at GPU, AI startup and cloud companies.

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Raju Gorla
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