Browsing: System Verilog

System Verilog

DPI in SystemVerilog: Calling C from Your Testbench (and Back)

Raju Gorla15 July 2026

SystemVerilog DPI explained with examples: importing C functions, exporting SystemVerilog tasks to C, context tasks, type mapping with svdpi.h, and using C++ and Python through DPI.

System Verilog

Functional Coverage in SystemVerilog: Covergroups, Bins and Crosses

Raju Gorla13 July 2026

How to write functional coverage in SystemVerilog: covergroups, coverpoints, bins, crosses, transition coverage, cover properties, where to sample and how to close coverage.

System Verilog

Constrained Randomisation in SystemVerilog: Constraints That Find Bugs

Raju Gorla10 July 2026

SystemVerilog constrained randomisation explained: rand and randc, constraint blocks, dist, implication, foreach, unique, soft, solve before, inline constraints and common mistakes.

System Verilog

Classes and OOP in SystemVerilog: Handles, Inheritance and Polymorphism

Raju Gorla9 July 2026

SystemVerilog classes for testbenches: objects and handles, shallow vs deep copy, encapsulation, inheritance, virtual methods and polymorphism, abstract classes and parameterised classes.